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New 4013 / XC4013E / XC4013EPQ240C / xilinx ic
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Please note: This spec sheet may cover several different parts. The spec sheet may also be from a manufacturer other than the manufacturer offered in this sale.
Information in this data sheet covers the XC4000E, XC4000EX, and XC4000XL families. A separate data sheet covers the XC4000XLA and XC4000XV families. Electrical Specifications and package/pin information are covered in separate sections for each family to make the information easier to access, review, and print. For access to these sections,see the Xilinx web site at
http:// /xlnx/xweb/xil_publications_index.jsp
• System featured Field-Programmable Gate Arrays
TM memory: on-chip ultra-fast RAM with
- Fully PCI compliant (speed grades -2 and faster)
- Flexible function generators
- Dedicated high-speed carry logic
- Wide edge decoders on each edge
- Hierarchy of interconnect lines
- Internal 3-state bus capability
- Eight global low-skew clock or signal distribution networks
• System Performance beyond 80 MHz
• Low Power Segmented Routing Architecture
- IEEE 1149.1-compatible boundary scan logic support
- Individually programmable output slew rate
- Programmable input pull-up or pull-down resistors
- 12 mA sink current per XC4000E output
• Configured by Loading Binary File
- Unlimited re-programmability
• Backward Compatible with XC4000 Devices
• Development System runs on most common computer platforms
- Interfaces to popular design environments
- Fully automatic mapping, placement and routing
- Interactive design editor for design optimization
Low-Voltage Versions Available
• Low-Voltage Devices Function at 3.0 - 3.6 Volts
• XC4000XL: High Performance Low-Voltage Versions of XC4000EX devices
Additional XC4000X Series Features
• High Performance — 3.3 V XC4000XL
• High Capacity — Over 180,000 Usable Gates
• 5 V tolerant I/Os on XC4000XL
• Additional Routing Over XC4000E
- almost twice the routing capacity for high-density designs
• Buffered Interconnect for Maximum Speed Blocks
TM I/O Interconnect for Better Fixed Pinout Flexibility
• 12 mA Sink Current Per XC4000X Output
• Flexible New High-Speed Clock Network
- Eight additional Early Buffers for shorter clock delays
- Virtually unlimited number of clock signals
• Optional Multiplexer or 2-input Function Generator on Device Outputs
• Four Additional Address Bits in Master Parallel Configuration Mode
